The present application concerns a television receiver having an integrated circuit with a built-in noise inverter circuit and external circuitry for defeating the operation of the noise inverter, e.g., in order to process a scrambled television signal.
In subscription television systems premium or pay television signals are transmitted "over the air", or via a cable network, or satellite in some scrambled form. Such signals are descrambled for viewing by means of a suitable decoder associated with the television receiver of an authorized system subscriber. The decoder is usually situated in a converter unit located external to the television receiver. The television signals may be grouped into several levels, or tiers, each representing a different programming category such as sporting events, movies, etc. The decoder of a particular subscriber is authorized to descramble the television signals in selected categories or channels, with the television signals in remaining unauthorized categories or channels being coupled to the television receiver in scrambled form.
A horizontal synchronization signal suppression technique is often used to scramble the television signal. In such a "suppressed sync" technique, scrambling is accomplished by suppressing the horizontal image synchronizing (sync) pulse component of the television signal. This causes the horizontal deflection system of the receiver to lock onto random video signal peaks during the active video line trace interval, rather than locking onto the actual horizontal sync pulses during the retrace interval, thereby producing an unstable and thereby unviewable displayed image.
Each system subscriber is provided with a decoder unit having a "front end" circuit which includes conventional tuning, intermediate frequency (IF) and video detection stages. Also, an automatic gain control circuit is provided within the decoder for controlling the gain of the tuning and IF stages in accordance with the output of the video detection stage. A sync restoration circuit operates during the suppressed sync pulse interval of the video signal developed at the output of the video detector stage for producing standard horizontal sync pulses. These sync pulses are continuously inserted in the video signal developed at the output of the video detector stage for producing a "descrambled" video signal suitable for viewing on a standard television receiver. The descrambled video signal with restored sync pulses is afterwards impressed on a standard television channel RF carrier signal by means of an RF modulator, and then coupled as a descrambled RF television signal to an antenna input of the television receiver.
Each decoder may additionally include a decode authorization circuit storing a unique subscriber code which is compared to a subscriber authorization code transmitted during a horizontal line of the vertical blanking interval of the television signal. If the stored subscriber code and the transmitted subscriber authorization code compare favorably, a decode authorization signal is developed for enabling the decoder, which is otherwise disabled.
Decoder systems for descrambling a suppressed sync video signal are discussed in U.S. Pat. No. 4,408,225 of Ensinger, et al., for example.
Television receivers commonly include a video signal responsive noise suppression circuit, such as a noise inverter, for suppressing noise pulses which occur during sync pulse intervals of the video signal by means of a signal inverting or equivalent technique. This action prevents noise pulses from disrupting the operation of subsequent sync separator circuits, and also prevents noise pulses from interfering with automatic gain control (AGC) action of the receiver.
The presence of a video signal responsive noise suppression circuit such as a noise inverter in a television receiver may adversely affect the processing of a scrambled television signal such as a suppressed sync signal. For example, in a suppressed sync type of scrambled signal, vertical blanking interval signal components should not be suppressed when the vertical blanking interval contains coded information, typically in digital (binary) form, for use by the scrambled signal decoder. The coded information may represent an authorization code for enabling the decoder to operate, a code which identifies the type of scrambling used, or a code which assists in the descrambling process in some other way.
In a video signal processing system which is subject to processing a scrambled video signal and which includes a noise suppression network such as a noise inverter responsive to video signals, it is desirable to include apparatus for defeating or disabling the operation of the noise suppression network during a descrambling operation to prevent distortion of coded information occurring during prescribed intervals such as vertical blanking intervals.
The size, cost and complexity of a decoder are increased by the need for the decoder to include an RF tuning stage, IF stage, video detector stage, AGC stage, and RF modulator, which stages (except for the modulator) duplicate stages already found in the "front end" of a television receiver. Thus it is desirable to provide a decoder which does not require such stages. Accordingly, the Electronic Industry Association (EIA) of the United States has proposed a decoder-receiver interface standard which simplifies the design of decoders for use in suppressed sync television signal systems for eliminating the need for the aforementioned tuning, IF, detector, AGC, and modulator stages in a suppressed sync decoder unit. As outlined in EIA Consumer Products Standard IS-15 "NTSC Television Receiver Audio/Video Baseband Interface Specification," the EIA decoder standard provides a mutually agreeable convention, to both television receiver manufacturers and the subscription TV industry, for the implementation of a standardized sync suppressed video decoder system.
One of the major impediments to implementation of the multiport standard has been the difficulty of disabling or defeating the operation of the noise inverter internally built into integrated circuits (ICs) commonly used in processing video signals in television receivers. Heretofore, specially designed integrated circuits had to be used which were designed for permitting the noise inverter to be selectively disabled or defeated. Approaches using such specially designed integrated circuits are described in U.S. Pat. No. 4,670,904 of the same inventor and is assigned to the predecessor of interest of the present assignee. In the arrangement described in the '904 patent, the operation of the noise inverter is selectively controlled by a comparator on the integrated circuit having a terminal accessible external to the IC for activation of the comparator in order to disable the noise inverter when the decoder is operating. Additionally, the magnitude of the AGC voltage is changed when the decoder is operative for activation of the comparator. However, this arrangement employs an IC specifically designed to provide for such selective disablement.
There are many video signal processing ICs which are commonly available for utilization in television receivers which do not have provisions for defeating the operation of the noise inverter and therefore do not lend themselves for use with a decoder.
Accordingly, it is desirable to be able to defeat the operation of the built-in noise inverter of a "standard" or "off-the-shelf" IC designed for video signal processing so that a receiver/decoder according to the EIA multiport standard can be implemented with such standard ICs.